One embodiment is directed towards a method. The method includes forming a drift region of a first conductivity type above or in a substrate. The substrate has first and second surfaces. A first insulator is formed over a first portion of the channel, and which has a first thickness. A second insulator is formed over the second portion of the channel, and which has a second thickness that is less than the first thickness. A first gate is formed over the first insulator. A second gate is formed over the second insulator. A body region of a second conductivity type is formed above or in the substrate.

A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source region and the drift region in the first direction, a plurality of planar insulation field plates disposed over the drift region and spaced apart from each other in a second direction, a plurality of trench insulation field plates disposed in the drift region, a gate insulation layer formed over the channel region, and a gate electrode formed over the gate insulation layer. Each of the trench insulation field plates is disposed between the planar insulation field plates in the second direction.

The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.

A p-type field effect transistor includes a pair of spacers over a substrate top surface. The p-type field effect transistor includes a channel recess cavity in the substrate top surface between the pair of spacers. The p-type field effect transistor includes a gate stack with a bottom portion in the channel recess cavity. The p-type field effect transistor includes a source/drain (S/D) recess cavity including a bottom surface and sidewalls below the substrate top surface, wherein the S/D recess cavity includes a portion extending below the gate stack. The p-type field effect transistor includes a strained material filling the S/D recess cavity. The p-type field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the bottom surface and sidewalls of the S/D recess cavity. The S/D extension includes a portion between the gate stack and the S/D recess cavity.

Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

A functional gate structure is located on a surface of a semiconductor material portion and including a U-shaped gate dielectric portion and a gate conductor portion. A source region is located on one side of the functional gate structure, and a drain region is located on another side of the functional gate structure. The source region and drain region both have a topmost surface that is above a topmost surface of the semiconductor material portion and another surface that touches a portion of the U-shaped gate dielectric. A contact structure is located on the topmost surface of the source region and/or the drain region. A middle-of-the-line air gap contact is located between the contact structure and the functional gate structure and above at least one of the source region and the drain region. The middle-of-the-line air gap contact is sealed by a portion of a conformal dielectric material.

A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.

A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.