Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.

A method of making a monolithic three dimensional NAND string is provided. A stack of alternating layers of a first material and a second material different from the first material is formed over a substrate. The stack is etched to form at least one opening in the stack. A charge storage material layer is formed on a sidewall of the at least one opening. A tunnel dielectric layer is formed on the charge storage material layer in the at least one opening. A semiconductor channel material is formed on the tunnel dielectric layer in the at least one opening. The first material layers are selectively removed to expose side wall of the charge storage material layer. A blocking dielectric is formed on the exposed side wall of the charge storage material layer. Control gates are formed on the blocking dielectric.

Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.

In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a select transistor and a control transistor laterally spaced apart over a substrate. A select gate electrode and a control gate electrode are disposed over a high-k gate dielectric layer and a memory gate oxide. A logic region is disposed adjacent to the memory region and has a logic device including a metal gate electrode disposed over the high-k gate dielectric layer and a logic gate oxide. The select gate electrode and the control gate electrode can be polysilicon electrodes.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first insulating region, and a memory portion. The first connector extends in a first direction. The first conductive layer is electrically connected to the first connector, and includes a first planar region, a first overlap region, a first side surface region, and a first crossing side surface region. The second connector extends in the first direction. The second conductive layer is electrically connected to the second connector, and includes a second planar region, a second overlap region, a second side surface region, and a second crossing side surface region. The first insulating region is provided between the first and second conductive layers. The memory portion is connected to the first and second planar regions.

This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction. Furthermore, this semiconductor device comprises a transistor electrically connected to the portion of the conductive layers. That transistor comprises: a channel layer extending in the first direction; a gate electrode layer disposed in a periphery of the channel layer; and a gate insulating layer disposed between the channel layer and the gate electrode layer.