Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

An embodiment high-density capacitor includes a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell and each of the plurality of vertical portions is vertically surrounded by the inner shell of a respective cylindrical portion of the bottom electrode. The surrounding portion of the top electrode respectively vertically surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode such that adjacent non-concentric cylindrical portions of the bottom electrode are separated from one another by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having a hexagonal symmetry.

A fabrication method is disclosed. The fabrication method includes: forming, on a substrate, a transistor comprising a source, drain, and gate; forming a multi-layer interconnection structure configured to provide electrical connections for the source, drain, and gate, wherein the multi-layer interconnection structure has a plurality of interconnection layers; forming a metal-insulator-metal (MiM) capacitor in the interconnection structure, the MiM capacitor comprising a first electrode, a high-K spacer with a first vertically-extending sidewall and a second vertically-extending sidewall wherein the first vertically-extending sidewall has a vertically extending interface with the first electrode, and a second electrode wherein the second vertically-extending sidewall has a vertically extending interface with the second electrode; forming a first conductive feature that connects to the first electrode; and forming a second conductive feature that connects to the second electrode.

A fabrication method includes: forming, above a substrate, a first electrode having a varying density that increases from a first density level at a bottom surface of the first electrode to a second density level that is higher than the first density level at a top surface of the first electrode; forming a high-K dielectric layer over the first electrode; and forming a second electrode over the HK dielectric layer having a varying density that increases from a third density level at a bottom surface of the second electrode that bonds to the HK dielectric layer to a fourth density level that is higher than the third density level at a top surface of the second electrode.

In an aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and forming a first semiconductor layer within the trench and along the sidewall. In an embodiment, the process can further include forming a barrier layer within the trench after forming the first semiconductor layer; forming a second semiconductor layer within the trench after forming the barrier layer, wherein within the trench, first and second portions of the second semiconductor layer contact each other adjacent to a vertical centerline of the trench; and exposing the second semiconductor layer to radiation sufficient to allow a void within second semiconductor layer to migrate toward the barrier layer. In another embodiment, after forming a semiconductor within the trench, the process can further include forming an insulating layer that substantially fills a remaining portion of the trench.

A method of fabricating a unit cell of a focal plane array includes providing an integrated circuit substrate, depositing a proximal portion of a dielectric layer on the substrate, and etching a plurality of recess structures into the dielectric layer. Each of the plurality of recess structures defines a partial via and includes sidewalls that extend from the first surface to a bottom portion of the respective recess structure. The method also includes forming a capacitor structure, depositing a distal portion of the dielectric layer on the capacitor structure and a region of the proximal portion of the dielectric layer, forming a plurality of vias passing to the capacitor structure, forming a metal layer, and forming a detector overlying the metal layer. The plurality of vias are positioned between the capacitor structure and the metal layer and electrically connect the capacitor structure to the metal layer.

A solid-state device includes a substrate with a stack of constituent thin-film layers that define an arrangement of electrodes and intervening layers. The constituent layers can conform to or follow a non-planar surface of the substrate, thereby providing a 3-D non-planar geometry to the stack. Fabrication employs a common shadow mask moved between lateral positions offset from each other to sequentially form at least some of the layers in the stack, whereby layers with a similar function (e.g., anode, cathode, etc.) can be electrically connected together at respective edge regions. Wiring layers can be coupled to the edge regions for making electrical connection to the respective subset of layers, thereby simplifying the fabrication process. By appropriate selection and deposition of the constituent layers, the multi-layer device can be configured as an energy storage device, an electro-optic device, a sensing device, or any other solid-state device.

Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.