A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor.

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing a semiconductor structure includes: forming a plurality of capacitor holes on a substrate, and exposing a part of the substrate on bottoms of the capacitor holes; forming a bottom electrode layer on surfaces of the capacitor holes; forming, on a surface of the bottom electrode layer, a dielectric layer continuously covering the surface of the bottom electrode layer; forming a first top electrode layer to continuously cover a surface of the dielectric layer by a first film forming process; by a second film forming process, forming, in a circumferential direction of the capacitor holes, a second top electrode layer continuously covering a surface of the first top electrode layer, and forming, in an axial direction of the capacitor holes.

The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).

A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

A method of fabricating a metal-insulator-metal (MIM) capacitor structure on a substrate includes forming a patterned metal layer over the substrate; forming an insulator layer over the patterned metal layer; forming a second metal layer over the insulator layer; removing part of the insulating layer and part of the second metal layer thereby forming a substantially coplanar surface that is formed by the patterned metal layer, the insulator layer, and the second metal layer; removing a portion of the second metal layer and a portion of the patterned metal layer to form a fin from the insulator layer that protrudes beyond the first metal layer and the second metal layer; and forming an inter-metal dielectric layer over the fin.

A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.