The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including a plurality of lower electrode pillars that are arranged at intervals; a dielectric layer, at least partially covering a sidewall of each of the lower electrode pillars; a first upper electrode, covering a surface of the dielectric layer; a first support layer, located above the plurality of lower electrode pillars, the dielectric layer, and the first upper electrode, wherein the first support layer at least exposes a peripheral region of a part of the first upper electrode.

There is provided a semiconductor device capable of improving performance and reliability of a device, by adjusting the arrangement of penetration patterns included in an electrode support for supporting the lower electrode. The semiconductor device includes a plurality of lower electrodes that are aligned with each other on a substrate along a first direction and a second direction different from the first direction, and a first electrode support that supports the lower electrodes, and includes a plurality of first penetration patterns, wherein the first electrode support includes a center region, and an edge region defined along a periphery of the center region, wherein the first penetration patterns include center penetration patterns that are spaced apart by a first interval in the center region, and wherein the first penetration patterns include edge penetration patterns that are spaced apart by a second interval different from the first interval in the edge region.

A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.

Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.

This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins.

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

A switched-capacitor DC-to-DC converter includes a logic cell and a capacitor cell vertically overlapping with the logic cell. The logic cell has a plurality of active elements disposed over a first substrate. The capacitor cell has a capacitor over a second substrate. A first interlayer insulation layer disposed over the first substrate is bonded to a second interlayer insulation layer disposed over the second substrate. A first through via connected to any one of interconnection patterns of the logic cell and a second through via connected to a lower electrode pattern of the capacitor cell are connected to each other through a first external circuit pattern. A third through via connected to an upper electrode pattern of the capacitor cell and a fourth through via connected to another one of the interconnection patterns of the logic cell are connected to each other through a second external circuit pattern.

Described are novel salts of the compound (3R,4R,5S)-5-(difluoromethyl) piperidine-3,4-diol, as well as methods of using the same for preventing and/or treating lysosomal storage disorders and/or degenerative disorders of the central nervous system. In particular, the present invention provides methods for preventing and/or treating Gaucher's disease and/or Parkinson's disease.

A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a contact plug in the dielectric layer. The method also includes partially removing the contact plug to form a recess over the contact plug. The method further includes forming a capacitor element in the recess.