A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.

A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

A semiconductor device includes a gate structure, an insulating layer and two source/drain regions. A portion of the gate structure is embedded in a substrate. The insulating layer is disposed between the portion of the gate structure and the substrate and encompasses the portion of the gate structure. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure.

A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.

A self-aligned transistor including an oxide semiconductor film, which has excellent and stable electrical characteristics, is provided. A semiconductor device is provided with a transistor that includes an oxide semiconductor film, a gate electrode overlapping with part of the oxide semiconductor film, and a gate insulating film between the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a first region and second regions between which the first region is positioned. The second regions include an impurity element. A side of the gate insulating film has a depressed region. Part of the gate electrode overlaps with parts of the second regions in the oxide semiconductor film.

A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.

The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.

A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions.