An influence of a gate interference is suppressed and a reverse recovery property of a diode is improved. A diode includes a diode region located between the first boundary trench and the second boundary trench and a first and second IGBT regions. An emitter region and a body region are provided in each of the first and second IGBT regions. Each body region includes a body contact portion. An anode region is provided in the diode region. The anode region includes an anode contact portion. An interval between the first and second boundary trenches is equal to or longer than 200 m. An area ratio of the anode contact portion in the diode region is lower than each of an area ratio of the body contact portion in the first IGBT region and an area ratio of the body contact portion in the second IGBT region.

A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.

A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n.sup.+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p.sup.+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p.sup.+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p.sup.-type region constituting an edge termination structure provided in the flat portion.

A semiconductor device includes a drift region extending from a first surface into a semiconductor portion. A body region between two portions of the drift region forms a first pn junction with the drift region. A source region forms a second pn junction with the body region. The pn junctions include sections perpendicular to the first surface. Gate structures extend into the body regions and include a gate electrode. Field plate structures extend into the drift region and include a field electrode separated from the gate electrode. A gate shielding structure is configured to reduce a capacitive coupling between the gate structures and a backplate electrode directly adjoining a second surface.

To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.

A semiconductor device includes first, second, third, and fourth electrodes, a first insulating film, and first, second third, and fourth silicon carbide layers. A first distance between the first electrode and a first interface between the fourth electrode and fourth silicon carbide region is longer than a second distance between the first insulating film and a second interface between the third silicon carbide region and the fourth silicon carbide region. The fourth silicon carbide region is between the third silicon carbide region and the second silicon carbide region in a direction perendicular to the second interface.

A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state. The device is configured such that the switching loss is different between at least two of the zones. Further, the device is configured such that zones having greater switching losses transition to the non-conducting state before zones having lesser switching losses.

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n region with a lower impurity concentration than the n-type drift region.

A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.