A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C). The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

A semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface. A field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body. The field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.

Switch devices using switch transistors with dual gates are provided. The dual gates may be controlled independently from each other by first and second gate driver circuits.

Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.

A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.

A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

A technique of reducing the manufacturing cost of a semiconductor device is provided, There is provided a method of manufacturing a semiconductor device comprising an ion implantation process of implanting at least one of magnesium and beryllium by ion implantation into a first semiconductor layer that is mainly formed from a group III nitride; and a heating process of heating the first semiconductor layer in an atmosphere that includes an anneal gas of at least one of magnesium and beryllium, after the ion implantation process.

The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N.sup.+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The Group III nitride-based HEMT includes a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, and a field plate structure.