A nitride semiconductor device includes a channel layer, a barrier layer made of Al.sub.xIn.sub.yGa.sub.1-x-yN (x>0, x+y1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer made of a nitride semiconductor selectively formed on the barrier layer in the active region, a gate electrode formed on the gate layer, a first insulating film that covers the gate electrode and that is in contact with the barrier layer in the active region, and a second insulating film that covers the first insulating film and that is in contact with the inactive region.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

A semiconductor device includes a semiconductor element, a first lead, a second lead and a connection lead. The semiconductor element includes an electron transit layer formed of a nitride semiconductor, an element obverse face and an element reverse face that are arranged to face opposite to each other in a thickness direction, and a gate electrode, a source electrode and a drain electrode that are disposed on the element obverse face. The drain electrode is bonded to the first lead. The source electrode is bonded to the second lead. The connection lead is connected to the second lead and disposed on the element reverse face so as to overlap with the semiconductor element as viewed in the thickness direction. The connection lead provides a conduction path for a principal current subjected to switching.

In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d.sub.1, a lower p-doped Group III nitride layer having a thickness d.sub.2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped Al.sub.xGa.sub.1-xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness d.sub.2 of the lower p-doped Group III nitride layer is larger than the thickness d.sub.1 of the upper p-doped GaN layer.

A nitride-based semiconductor device includes a substrate, a buffer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a S/D electrode, a second S/D electrode, and a gate electrode. The buffer is disposed over the substrate and includes at least one layer of a nitride-based semiconductor compound doped with an acceptor at a top-most portion of the buffer. The first and second nitride-based semiconductor layers are disposed over the buffer. The first S/D electrode is disposed over the second nitride-based semiconductor layer, in which the first S/D electrode extends downward to a position lower than the first nitride-based semiconductor layer, so as to form at least one first interface with the top-most portion of the buffer, making contact with the at least one layer of the nitride-based semiconductor compound. The second S/D electrode and the gate electrode are disposed over the second nitride-based semiconductor layer.

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode, a first electrode, a first via and a second via. The substrate has a first surface and a second surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap exceeding that of the first nitride semiconductor layer. The gate electrode and the first electrode are disposed on the second nitride semiconductor layer. The first via extends from the second surface and is electrically connected to the first electrode. The second via extends from the second surface. The depth of the first via is different from the depth of the second via.

A semiconductor device includes a drain electrode, a first source electrode, a second source electrode, a first gate electrode, and a second gate electrode. The first gate electrode is arranged between the first source electrode and the drain electrode. The first gate electrode extends along a first direction. The second gate electrode is arranged between the second source electrode and the drain electrode. The second gate electrode extends along the first direction. The first gate electrode is arranged above a first imaginary line substantially perpendicular to the first direction in a top view of the semiconductor device and the second gate electrode is arranged below a second imaginary line substantially perpendicular to the first direction in the top view of the semiconductor device.

A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.

Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in package body comprising dielectric layers and electrically conductive layers, and where an external dielectric coating, such as a solder resist coating is provided on one or both external sides of the package body. The solder resist coating is patterned to avoid inside corners, e.g. the solder resist does not extend around or between electrical contact areas and thermal pads. It is observed that in conventional solder resist coatings, during thermal cycling, cracks tend to initiate at high stress points, such as at sharp inside corners. A solder resist layout which omits inside corners, and comprises outside corners only, is demonstrated to provide significantly improved resistance to initiation and propagation of cracks. Where inside corners are unavoidable, they are appropriately radiused to reduce stress.

A layer of yttrium (Y) and aluminum nitride (AlN) is employed as a back-barrier to improve confinement of electrons within a channel layer of a high electron mobility transistor (HEMT). As HEMT dimensions are reduced and a channel length decreases, current control provided by a gate also decreases, and it becomes more difficult to pinch-off current flow through the channel. A back-barrier layer on a back side of the channel layer improves confinement of electrons to improve pinch-off but does not cause a second 2DEG to be formed below the back-barrier layer. The YAlN layer can be lattice-matched to the channel layer to avoid lattice strain, and a thin layer of YAlN provides less thermal resistance than HEMTs made with thicker back-barrier materials. Due to its chemical nature, a YAlN layer can be used as an etch stop layer.