A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate, and a drain region disposed within the substrate and separated from the source region. A plurality of separate isolation structures are disposed within the substrate. The plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another. A gate electrode is disposed within the substrate. The gate electrode includes a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of separate isolation structures.

A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

Semiconductor devices including a high-k field relief dielectric structure are described. The microelectronic device comprises a substrate including a body region and a drain drift region on the substrate, a gate dielectric layer extending over the body region and the drift region, a drain drift trench is formed by removal of silicon dioxide from a LOCOS silicon region, a high-k field relief dielectric structure laterally abutting the gate dielectric layer at a location in the drift region, and a gate electrode on the gate dielectric layer and the field relief dielectric layer. Increasing the dielectric constant of the field relief dielectric structure may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance. A drain drift trench formed in a trench left after removal of silicon dioxide in a LOCOS region provides improved trench depth uniformity.

A semiconductor device can include: a substrate; a well region located in the substrate and having a first doping type; a body region located in the substrate and having a second doping type that is opposite to the first doping type; a source region located in the body region and having the first doping type; a drain region located in the well region and having the first doping type; an isolation structure located on the substrate and between the drain region and the source region; and a gate structure located on the isolation structure and including a first gate region and a second gate region, where the first gate region is of the first doping type, and the second gate region is of the second doping type.

A high voltage device includes drift regions formed in a substrate, an isolation layer formed in the substrate to isolate neighboring drift regions, wherein the isolation layer has a depth greater than that of the drift region, a gate electrode formed over the substrate, and source and drain regions formed in the drift regions on both sides of the gate electrode.

A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.