A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.

One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.

A semiconductor device includes a first conductive type first main electrode region, a first conductive type drift region which makes contact with the first main electrode region, a first conductive type second main electrode region which makes contact with the drift region, a second conductive type well region which is provided in a part of a surface layer portion of the drift region and to which a reference potential is applied, and a first conductive type potential extracting region which is provided in a surface layer portion of the well region and to which the reference potential is applied. The well region serves as a base region which controls a current flowing between the potential extracting region and the drift region. Thus, it is possible to provide a novel semiconductor device which is high in reliability while the increase of the chip size can be suppressed.

A device layer of an integrated circuit device includes a semiconductor active layer spanning a plurality of device regions. Each of the device regions has a heating element, a temperature sensor, and bioFETs in the device layer. The bioFETs have source/drain regions and channel regions in the semiconductor active layer and fluid gates exposed on a surface for fluid interfacing on one side of the device layer. A multilayer metal interconnect structure is disposed on the opposite side of the device layer. This structure places the heating elements in proximity to the fluid gates enabling localized heating, precision heating, and multiplexed temperature control for multiplexed bio-sensing applications.

A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.

A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH.sub.3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a room mean square (rms) roughness of <10 and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square m with an average pit diameter less than (<) 0.05 m.

A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

A Dual-wavelength hybrid (DWH) device includes an n-type ohmic contact layer, cathode and anode terminal electrodes, first and second injector terminal electrodes, p-type and n-type modulation doped QW structures, and first through sixth ion implant regions. The first injector terminal electrode is formed on the third ion implant region that contacts the p-type modulation doped QW structure and the second injector terminal electrode is formed on the fourth ion implant region that contacts the n-type modulation doped QW structure. The DWH device operates in at least one of a vertical cavity mode and a whispering gallery mode. In the vertical cavity mode, the DWH device converts an in-plane optical mode signal to a vertical optical mode signal, whereas in the whispering gallery mode the DWH device converts a vertical optical mode signal to an in-plane optical mode signal.

A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.