A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.

A method of fabricating a semiconductor device comprises providing a substrate with a shallow trench isolation (STI) within the substrate and a gate stack. A cavity is formed between the gate stack and the STI. The cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate. A film is grown in the cavity and thereafter an opening formed by removing a first portion of the strained film until exposing the bottom surface of the substrate while a second portion of the strained film adjoins the STI sidewall. Another epitaxial layer is then grown in the opening.

A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral growth channel and a fin seed structure arranged in the lateral growth channel. The fin seed structure provides a seed surface for growing a fin structure. One or more first semiconductor structures of a first semiconductor material and one or more second semiconductor structures of a second, different, semiconductor material are grown sequentially in the growth channel from the seed surface in an alternating way. The first semiconductor structures provide a seed surface for the second semiconductor structures and the second semiconductor structures provide a seed surface for the first semiconductor structures. The second semiconductor structures are selectively etched, thereby forming the fin structure comprising a plurality of parallel fins of the first semiconductor structures. Corresponding semiconductor structures are also included.

A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with AlGaN, and the third semiconductor layer has a lower composition ratio of Al than that of the second semiconductor layer.

A semiconductor device includes first to third electrodes, a semiconductor member, first and second insulating members, a compound member, and a nitride member. The third electrode is between the first and second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes first and second insulating portions. The first semiconductor portion is between the fourth partial region and the first insulating portion. The second semiconductor portion is between the fifth partial region and the second insulating portion. The compound member includes first to third compound portions. The nitride member includes first to third nitride portions. The second insulating member includes first and second insulating regions. The first and second insulating regions are between the nitride regions and the third electrode.

A semiconductor device includes first to third electrodes, a semiconductor member, first and second insulating members, a compound member, and a nitride member. The third electrode is between the first and second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes first and second insulating portions. The first semiconductor portion is between the fourth partial region and the first insulating portion. The second semiconductor portion is between the fifth partial region and the second insulating portion. The compound member includes first to third compound portions. The nitride member includes first to third nitride portions. The second insulating member includes first and second insulating regions. The first and second insulating regions are between the nitride regions and the third electrode.

The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

Disclosed in an embodiment is a semiconductor device comprising a semiconductor structure, which comprises a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein: the first conductive semiconductor layer comprises a first super lattice layer comprising a plurality of first sub layers and a plurality of second sub layers, the first and second sub layers being alternately arranged; the semiconductor structure emits ions of indium, aluminum, and a first and second dopant during a primary ion irradiation; the intensity of indium ions emitted from the active layer includes a maximum indium intensity peak; the doping concentration of the first dopant emitted from the first conductive semiconductor layer includes a maximum concentration peak; the maximum indium intensity peak is disposed to be spaced from the maximum concentration peak in a first direction; the intensity of indium ions emitted from the plurality of first sub layers has a plurality of first indium intensity peaks; the doping concentration of the first dopant emitted from the plurality of first sub layers has a plurality of first concentration peaks; and the plurality of first indium intensity peaks and the plurality of first concentration peaks are disposed between the maximum indium intensity peak and the maximum concentration peak.