The present invention provides a PSVA liquid crystal display panel, comprising an upper substrate (1), a lower substrate (2) oppositely located to the upper substrate (1) and a liquid crystal layer (3) located between the upper substrate (1) and the lower substrate (2); the lower substrate (2) comprises a second substrate (21), a thin film transistor, a passivation layer (22) and a pixel electrode (23); the lower substrate (2) comprises a plurality of pixel areas, and the passivation layer (22) is a passivation layer which is patterned, and is respectively formed the same pattern corresponding to the plurality of pixel areas, and the pattern comprises a plurality of trenches (221) extending toward various directions; the pixel electrode (23) is entirely attached to the passivation layer (22) which is patterned and comprises a corresponding pattern with the passivation layer (22); a depth of the trench (221) is 2000-4000 . The PSVA liquid crystal display panel of the present invention possesses higher transmittance and excellent optical performance.

A display device includes: a light-emitting element at a display area; a driving element electrically connected to the light-emitting element; an encapsulation layer covering the light-emitting element; a touch sensor on the encapsulation layer; a connection pad at a bonding area, the connection pad including a lower conductive layer, an intermediate conductive layer on the lower conductive layer, and an upper conductive layer on the intermediate conductive layer; a cladding layer covering at least a side surface of the intermediate conductive layer and including an organic material; a passivation layer covering an upper surface of the cladding layer and including an inorganic material, a portion of the passivation layer being located under the upper conductive layer; and a driving circuit attached to the connection pad.

A display device includes: a substrate; a polycrystalline silicon film on the substrate; and a first buffer film between the substrate and the polycrystalline silicon film and having one surface contacting the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first root mean square (RMS) roughness range, and the first RMS roughness range is 1.5 nm or less.

A display device and a manufacturing method thereof are provided. The display device includes a display area and a non-display area. The display device includes a substrate, an element layer, an electrode pattern layer, a photoresist pattern layer, and a light-emitting element. The element layer is disposed on the substrate. The electrode pattern layer is disposed on the element layer, and the electrode pattern layer includes multiple electrodes. The photoresist pattern layer is disposed on the electrode pattern layer, and the photoresist pattern layer includes a first photoresist pattern disposed corresponding to the display area and corresponding to the electrodes; a second photoresist pattern disposed corresponding to the non-display area and between the electrodes. The light-emitting element is disposed on the photoresist pattern layer and is electrically connected to the electrodes of the electrode pattern layer.

Provided are an array substrate and a display apparatus thereof. The array substrate includes a display region and a binding region located at a side of the display region; the binding region includes a first conductive layer disposed on the substrate and a planarization layer disposed at a side of the first conductive layer away from the substrate. The binding region includes a binding zone and a vacancy zone alternately disposed along an edge of the display region, the first conductive layer includes a plurality of binding pins disposed in the binding zone, and the planarization layer is provided with first openings exposing the plurality of binding pins and covering the binding zone and the vacancy zone.

A display device includes a first substrate arranged with a plurality of pixels on a first surface, the plurality of pixels having a display element including a transistor, and a first wiring connected to the transistor, a through electrode arranged in a first contact hole reaching the first wiring from a second surface facing the first surface of the first substrate, a second wiring connected with the through electrode, a first insulation film arranged covering the second wiring on the second surface of the first substrate, and a terminal connected with a second wiring via a second contact hole arranged in the first insulation film.

A display substrate, a method for fabricating the same, and a display device are disclosed. The display substrate comprises a plurality of pixels; and a plurality of slit patterns, which are arranged between at least two of the plurality of pixels, and comprise a plurality of slits arranged in a rubbing direction. Slit patterns are provided, and each of slit patterns comprises slits in the rubbing direction. Thus, during a rubbing alignment process, the slit patterns can guide a rubbing cloth to move in the rubbing direction. Accordingly, the alignment of the rubbing cloth is prevented from changing in the rubbing process, a good alignment layer is formed, rubbing Mura is avoided, and the lifetime of the rubbing cloth is extended.

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Manufacturing method including forming, over substrate, TFT layer, planarization layer, and display element in this order. Forming of TFT layer involves forming passivation layer to cover TFT layer electrode, such as upper electrode, and to come in contact with planarizing layer. Forming of display element involves forming bottom electrode to come in contact with planarizing layer. TFT layer electrode and bottom electrode are connected by: first forming, in planarizing layer, first contact hole exposing passivation layer at bottom thereof; then forming second contact hole exposing TFT layer electrode at bottom thereof through dry-etching passivation layer exposed at bottom of first contact hole using fluorine-containing gas; then forming liquid repellent film containing fluorine on passivation layer inner surface facing second contact hole; and forming bottom electrode along planarizing layer inner surface and passivation layer inner surface respectively facing first contact hole and second contact hole.

A display may have an array of pixels formed from organic light-emitting diodes and thin-film transistor circuitry. A planarization layer may be interposed between the thin-film transistor circuitry and the organic light-emitting diodes. To protect the organic light-emitting diodes from photoactive compounds that may be outgassed from the planarization layer, an inorganic barrier layer may be interposed between the planarization layer and the organic light-emitting diodes. The inorganic barrier layer may be formed on top of and/or below a pixel definition layer that defines light-emitting zones for the organic light-emitting diodes. In another suitable arrangement, the inorganic barrier layer may itself define light-emitting zones and may be used in place of a polymer-based pixel definition layer. The inorganic barrier layer may include trenches in which the emissive material of the light-emitting diodes is formed.