A semiconductor device includes a plurality of gate caps over a plurality of gate regions, gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, a backside contact under a first source and drain region and a dielectric cap over the first source and drain region. The first source and drain region is located between two adjacent gate regions of the plurality of gate regions.

A semiconductor device including a semiconductor substrate. A first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. A CA layer forms a local interconnect layer electrically connected to one of the source and the drain of the first transistor. A CB layer forms a local interconnect layer electrically connected to the gate of one of the first transistor and the second transistor. An end of the CB layer is disposed at a center of the CA layer

Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.

A field effect transistor having a higher breakdown voltage can be provided by forming a contiguous dielectric material layer over gate stacks, forming via cavities laterally spaced from the gate stacks, selectively depositing a single crystalline semiconductor material, and converting upper portions of the deposited single crystalline semiconductor material into elevated source/drain regions. Lower portions of the selectively deposited single crystalline semiconductor material in the via cavities can have a doping of a lesser concentration, thereby effectively increasing the distance between two steep junctions at edges of a source region and a drain region. Optionally, embedded active regions for additional devices can be formed prior to formation of the contiguous dielectric material layer. Raised active regions contacting a top surface of a substrate can be formed simultaneously with formation of the elevated active regions that are vertically spaced from the top surface.

A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.