A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of a third conductive structure. A fourth transistor has a gate electrode formed by a substantially linear portion of a fourth conductive structure. The substantially linear portions of the first, second, third, and fourth conductive structures extend in a first direction and are positioned in accordance with a gate pitch. Gate electrodes of the first and second transistors have a first size as measured in the first direction. Gate electrodes of the third and fourth transistors have a second size as measured in the first direction. The first size is at least two times the second size.

A method for manufacturing an array substrate, including steps of forming a semiconductor pattern, a gate electrode and a first insulation pattern sequentially on a base substrate at different layers, an orthogonal projection of the semiconductor pattern onto the base substrate covering an orthogonal projection of the first insulation pattern onto the base substrate, and the orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate, and subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, so as to form an active layer, a heavily-doped source electrode region, a lightly-doped source electrode region, a heavily-doped drain electrode region, and a lightly-doped drain electrode region.

A semiconductor device includes a fin-shaped silicon layer on a silicon substrate surface. The fin-shaped silicon layer has a longitudinal axis extending in a first direction parallel to the surface and a first insulating film is around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, and a pillar diameter of the bottom of the pillar-shaped silicon layer is equal to a fin width of the top of the fin-shaped silicon layer. The pillar diameter and the fin width are parallel to the surface. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and has a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer.

A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm.

More stable perpendicular magnetization orientation is attained, and switching of the magnetization orientation between an out-of-plane direction and an in-plane direction is enabled by voltage. A multiferroic laminated structure having ferroelectricity and ferromagnetism includes: a ferroelectric layer made of a ferroelectric substance having the ferroelectricity; a foundation layer composed mainly of a metal having a good lattice-matching property with the ferroelectric substance and laminated on a surface of the ferroelectric layer; an intermediate layer composed mainly of a non-magnetic substance and laminated on a surface of the foundation layer; and a ferromagnetic/non-magnetic multilayer film layer constituted by alternately laminating ferromagnetic layers and non-magnetic layers on a surface of the intermediate layer in at least three cycles, the ferromagnetic layers being composed mainly of a ferromagnetic substance, the non-magnetic layers being composed mainly of the non-magnetic substance.

The disclosed technology generally relates to sensors comprising a two-dimensional electron gas (2DEG), and more particularly to an AlGaN/GaN 2DEG-based sensor for sensing signals associated with electrocardiograms, and methods of using the same. In one aspect, a sensor comprises a substrate and a GaN/AlGaN hetero-junction structure formed on the substrate and configured to form a two-dimensional electron gas (2DEG) channel within the GaN/AlGaN hetero-junction structure. The sensor additionally comprises Ohmic contacts connected to electrical metallizations and to the 2DEG channel, wherein the GaN/AlGaN hetero-junction structure has a recess formed between the Ohmic contacts. The sensor further comprises a dielectric layer formed on a top surface of the sensor.

A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.

A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench.

A manufacturing method of an array substrate includes: providing a first substrate; forming a gate line, a data line, and a thin-film transistor array on the first substrate; forming a pixel electrode on the thin-film transistor array; depositing and forming a first passivation layer on the pixel electrode, the data line, and the thin-film transistor array; forming a black matrix on the first passivation layer; and forming a common electrode on the black matrix and the first passivation layer. The black matrix has a size that completely covers at least the data line such that when the common electrode is formed on the black matrix and the first passivation layer, a portion of the common electrode that corresponds exactly to the data line is completely spaced from the data line by the black matrix and the first passivation layer.