A non-active gate structure is formed over a shallow trench isolation (STI) region that is adjacent to at least one fin structure of a semiconductor device that includes a fin-based transistor. The non-active gate structure includes at least one support structure that extends from the gate in a direction that is approximately orthogonal to the direction in which the main body of the non-active gate structure extends. The support structure provides structural support for the non-active gate structure, which increases the stability of the non-active gate structure relative to a gate structure that does not include the support structure.

A method includes providing a workpiece. The workpiece includes a substrate, a fin protruding from the substrate, and a dummy gate structure over the fin. The method further includes performing an oxidizing process to exposed surfaces of the fin and the dummy gate structure to form an oxide layer thereon, removing the oxide layer to expose an unoxidized top surface and sidewalls of the fin and unoxidized sidewalls of the dummy gate structure, epitaxially growing a cap layer on the unoxidized top surface and sidewalls of the fin and the unoxidized sidewalls of the dummy gate structure, forming a source/drain feature on the fin, and replacing the dummy gate structure with a metal gate structure.

A method for fabricating semiconductor devices is disclosed. The method includes forming a first fin structure and a second fin structure in a first region and a second region of a substrate, respectively, wherein the first and second fin structure and the substrate comprise a first semiconductor material; forming a first liner structure and a second liner structure at least extending along sidewalls of the first fin structure and sidewalls of the second fin structure, respectively; replacing an upper portion of the second fin structure with a second semiconductor material, while leaving the first fin structure substantially intact; and exposing a top surface and upper sidewalls of the first fin structure, and a top surface and upper sidewalls of the second fin structure.

A semiconductor device includes a semiconductor fin protruding from a substrate. The semiconductor device includes a P-type device over the semiconductor fin and an N-type device over the semiconductor fin. The P-type device includes a first source/drain (S/D) feature adjacent a first gate structure. The P-type device includes a dipole layer over the first S/D feature, where the dipole layer includes a first metal and a second metal different from the first metal. The P-type device further includes a first silicide layer over the dipole layer, where the first silicide layer includes the first metal. The N-type device includes a second S/D feature adjacent a second gate structure. The N-type device further includes a second silicide layer directly contacting the second S/D feature, where the second silicide layer includes the first metal, and where a composition of the second silicide layer is different from that of the dipole layer.

A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a source region, a drain region, a channel region and a plurality of fins. The channel region is located between the source region and the drain region, and the fins pass through the source region, the drain region and the channel region, wherein a number of the fins located in the source region and the drain region and a number of the fins located in the channel region are not equal.

A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.