The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

A method includes forming a plurality of fin structures extending along a first direction. The method includes forming a dummy fin structure disposed between two adjacent fin structures. The dummy fin structure also extends along the first direction and includes a deformable layer. The method includes recessing portions of each fin structure. The method includes forming source/drain structures over the recessed fin structures. The method includes deforming the deformable layer of the dummy fin structure to apply either a tensile stress or a compressive stress on the source/drain structures coupled to each of the two adjacent fin structures.

A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

A device with stacked transistors includes a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, and a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods. The source block of the second transistor is distinct from the source and drain block of the second transistor, and the drain block of the second transistor is distinct from the drain and source blocks of the second transistor.

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.

A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

A filler cell region (in a semiconductor device) includes: gate segments, a majority of first ends of which substantially align with a first reference line that parallel and proximal to a top boundary of the filler cell region, and a majority of second ends of which substantially align with a second reference line that is parallel and proximal to a bottom boundary of the filler cell region. First and second gate segments extend continuously across the filler cell region; and third & fourth and fifth & sixth gate segments are correspondingly coaxial and separated by corresponding gate-gaps. Relative to the first direction: a first end of the first gate segment extends to the top boundary of the filler cell region; and a second end of the second gate segment extends to the bottom boundary of the filler cell region.

A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.

A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.