Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.

An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.

A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.