Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

A semiconductor device comprises a transistor device arranged on a substrate. The transistor device comprises a first metal gate stack arranged over a channel region, a source/drain region arranged adjacent to the metal gate stack, the source/drain region located on a fin, and a capacitor device arranged on the substrate. The capacitor device comprises a second metal gate stack arranged on the substrate, a spacer arranged along a sidewall of the second metal gate stack, and a first conductive contact arranged on the substrate adjacent to the spacer such that the spacer is disposed between the first conductive contact and the second metal gate stack.

A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110>orientation wherein the hard mask is oriented in the <112>direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

Vertical channel field effect transistors and methods of forming the same include forming one or more vertical channels on a bottom source/drain layer. A seed layer is deposited on horizontal surfaces around the one or more vertical channels. A metal gate is deposited on the seed layer. A top source/drain layer is deposited above the one or more vertical channels and the metal gate.

A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.

The semiconductor device including: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region, a gate extending on the semiconductor layer to cover the channel region, and a gate dielectric layer interposed between the channel region and the gate, a corner insulating spacer having a first surface and a second surface, the first surface extending in the second direction along a side wall of the gate, the first surface covering from a side portion of the gate dielectric layer to at least a portion of the side wall of the gate, and the second surface covering a portion of the semiconductor layer, and an outer portion insulating spacer covering the side wall of the gate above the corner insulating spacer, the outer portion insulating spacer having a smaller dielectric constant than the corner insulating spacer, may be provided.

A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.