A method of forming an electronic device includes forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET). The interface layer is between the dielectric layer and a substrate of the FET. The method further includes forming a dipole layer by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer.

A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.

A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, an etch stop layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer.

A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Embodiments of the present invention provide methods for fabricating a semiconductor device with buried local interconnects. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a first set of spacers along the sides of the fins; depositing a tungsten film over the top surface of the substrate; etching the tungsten film to form a buried local interconnect; forming a set of gates and a second set of spacers; forming a source and drain region adjacent to the fins; depositing a first insulating material over the top surface of the substrate; and creating contact between the set of gates and the source and drain region using an upper buried local interconnect.

A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the nanosheet stack; forming a first spacer along a sidewall of the gate stack; removing an endwall portion of the nanosheet stack that extends beyond the first spacer such that a portion of the second layer is exposed from a sidewall of the first spacer; depositing a second spacer along a sidewall of the first spacer; recessing the substrate beneath the second spacer to form an isolation region; depositing an oxide on the gate stack and within the isolation region and partially recessing the oxide; removing a portion of the second spacer such that the portion of the second layer is exposed; and growing an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region.

A semiconductor device comprises a transistor device arranged on a substrate. The transistor device comprises a first metal gate stack arranged over a channel region, a source/drain region arranged adjacent to the metal gate stack, the source/drain region located on a fin, and a capacitor device arranged on the substrate. The capacitor device comprises a second metal gate stack arranged on the substrate, a spacer arranged along a sidewall of the second metal gate stack, and a first conductive contact arranged on the substrate adjacent to the spacer such that the spacer is disposed between the first conductive contact and the second metal gate stack.