A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

An integrated circuit includes a drain in a substrate, wherein the drain comprising a doped drain well. The doped drain well includes a first zone, wherein the first zone has a first concentration of a first dopant; and a second zone, wherein the second zone has a second concentration of the first dopant, a top-most surface of the first zone is coplanar with a top-most surface of the second zone, and the first concentration is different from the second concentration. The integrated circuit further includes a gate electrode over the substrate, the gate electrode being separated from each of the first zone and the second zone in a direction parallel to a top surface of the substrate by a distance greater than 0.

A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

A semiconductor fabrication method includes: forming, on a substrate, an epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on channel regions of the fin; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; performing pre-treatment operations to remove impurities from the at least one sacrificial epitaxial layer; recessing the at least one sacrificial epitaxial layer to form a cavity; forming inner spacer material in the cavity; forming source/drain features; removing the sacrificial gate stack and the at least one sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and the at least one sacrificial epitaxial layer, wherein the inner spacers have sufficient thickness to resist epi damage.

Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an inner spacer layer between two adjacent nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the inner spacer layer, and a barrier layer adjacent to the inner spacer layer. The barrier layer extends from the first position to the second position, and the first position is between the inner spacer layer and the nanostructure, and the second position is between the nanostructures and the S/D structure.

A semiconductor device may include first and second bit lines that each include a line portion, a connection portion extending from the line portion into a first extension region, and a pad portion extending from the connection portion in the first extension region; and a third bit line between the line portions of the first and second bit lines in a memory cell array region and the first extension region. A first end portion of the third bit line may be in the first extension region. The pad portions of the first and second bit lines each may be wider than the line portions of the first and second bit lines. A minimum distance between the pad portions of the first and second bit lines may be less than a minimum distance between the line portion of the first bit line and the third bit line.

Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

Wide bandgap trench gate semiconductor devices are provided. In one example, a semiconductor device includes a wide bandgap semiconductor structure. The wide bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench in the wide bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes a buried gate structure in the gate trench. The buried gate structure includes a gate polysilicon layer and a gate silicide layer.