A semiconductor device including a substrate; a continuous buried oxide layer (BOX) formed on the substrate; and a plurality of nanosheet gate-all-round (GAA) device structures on the BOX, wherein a first plurality of stacked gates of the nanosheet GAA device structures are disposed in a logic portion of the substrate and have a first nanosheet width, wherein a second plurality of stacked gates of the nanosheet GAA device structures are disposed in a high density region of the substrate and have a second nanosheet width less than the first nanosheet width, wherein the nanosheet GAA device structures are disposed directly on the continuous buried oxide layer, and wherein a bottom layer of the nanosheet GAA device structures is a bottom gate formed directly on the BOX.

A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a pulse width modulation (PWM) signal from an inverter controller and adjust the received PWM signal based on a feedback signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to receive the adjusted PWM signal from the low voltage phase controller, provide the adjusted PWM signal to a phase switch, and provide the feedback signal based on an on-time measurement of the phase switch.

The present disclosure describes semiconductor devices and methods for forming the same. A semiconductor device includes nanostructures over a substrate and a source/drain region in contact with the nanostructures. The source/drain region is doped with a first-type dopant. The semiconductor device also includes a counter-doped structure in contact with the substrate and the source/drain region. The counter-doped structure is doped with a second-type dopant opposite to the first-type dopant.

A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a first power module including: a first connection; a second connection; a first power switch including a first gate terminal, the first power switch configured to control a first flow of current between the first connection and the second connection based on a first signal to the first gate terminal; and a first point-of-use controller configured to provide the first signal to the first gate terminal to control the first power switch.

An integrated circuit includes a device region and an overlay mark region. The device region includes a plurality of stacked channels of a transistor, a source/drain region of the transistor, a source/drain contact of a first material on the source/drain region, and a conductive via of a second material in contact with the source/drain contact. The overlay mark region includes a first diffraction grating of first metal structures of the first material and a second first diffraction grating of second metal structures above of the second material above and offset from the first metal structures.

A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl.sub.3).sub.2CH.sub.2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets; an inner sidewall spacer adjacent each of the plurality of gate structures; and corner spacers under the plurality of stacked semiconductor nanosheets.

A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure. The method also includes forming a gate stack wrapped around the first fin structure and the second fin structure. The method further includes simultaneously removing the sacrificial layers of the first fin structure and the second fin structure. Remaining portions of the semiconductor layers of the first fin structure form multiple first semiconductor nanostructures, and remaining portions of the semiconductor layers of the second fin structure form multiple second semiconductor nanostructures. Each of the first semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.

Provided is a three-dimension (3D) stacked semiconductor device which includes: a 1.sup.stsource/drain region connected to a 1.sup.st channel structure; and a 2.sup.nd source/drain region, above the 1.sup.st source/drain region, connected to a 2.sup.nd channel structure above the 1.sup.st channel structure, wherein the 2.sup.nd channel structure has a smaller length than the 1.sup.st channel structure in a channel-length direction, in which the 2.sup.nd source/drain region is connected to a 3.sup.rd source/drain region through the 2.sup.nd channel structure.