In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.

Semiconductor devices and corresponding methods of manufacture are disclosed. The devices may include a first epitaxial structure disposed below a dielectric pillar, a second epitaxial structure disposed above the first epitaxial structure and around the dielectric pillar, a third epitaxial structure disposed above the second epitaxial structure and around the dielectric pillar, and a fourth epitaxial structure disposed above the third epitaxial structure and around the dielectric pillar. The second and third epitaxial structures may each have a portion inwardly extending toward a central axis of the dielectric pillar.

A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.

A method for forming a semiconductor structure is provided. The method includes forming a first nanostructure and a second nanostructure over a substrate, forming a first interfacial layer on the first nanostructure and a second interfacial layer on the second nanostructure, forming a first gate dielectric layer on the first interfacial layer and a second gate dielectric layer on the second interfacial layer, forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer, and driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer.

A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.

This application provides a test structure and a method for calibrating gate parasitic capacitance. A first test structure can calibrate a dimension and thickness table related to a first metal layer in an ITF file. A second test structure is formed by an MOS structure after removing contact holes in source/drain regions, and this structure is used for calibrating gate dimension and thickness values in the ITF file. A third test structure is formed by the MOS structure after removing metal interconnect lines in source/drain regions, removing shallow doped source/drain regions composed of first conductive type lightly-doped regions, and this structure is used for calibrating tables related to capacitance Cco and Cf in the ITF file. A fourth test structure is an MOS structure, and its actual capacitance test result is compared with a simulation result to ensure that the gate parasitic capacitance conforms to the model simulation.

To manufacture a semiconductor electronic device a wafer is provided that has a substrate layer of semiconductor material having a first portion and a second portion distinct from the first portion. An epitaxial region of a single semiconductor material is grown on the first portion of the substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based upon the single semiconductor material is formed starting from the epitaxial region and a second electronic component based upon a heterostructure is formed starting from the heterostructure. To grow an epitaxial multilayer, a growth mask is formed on the substrate layer; an opening is made in the growth mask, thereby exposing the second portion of the substrate layer; and the epitaxial multilayer is grown on the second portion of the substrate layer.

A semiconductor device including a semiconductor substrate. A first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. A CA layer forms a local interconnect layer electrically connected to one of the source and the drain of the first transistor. A CB layer forms a local interconnect layer electrically connected to the gate of one of the first transistor and the second transistor. An end of the CB layer is disposed at a center of the CA layer

A semiconductor device with a high on-state current is provided. A transistor included in the semiconductor device includes a first insulator; a first semiconductor layer over the first insulator; a second semiconductor layer including a channel formation region over the first semiconductor layer; a first conductor and a second conductor over the second semiconductor layer; a second insulator over the second semiconductor layer and between the first conductor and the second conductor; and a third conductor over the second insulator. In a cross-sectional view in a channel width direction of the transistor, the third conductor covers a side surface and a top surface of the second semiconductor layer. The second semiconductor layer has a higher permittivity than the first semiconductor layer. In the cross-sectional view in the channel width direction of the transistor, a length of an interface between the first semiconductor layer and the second semiconductor layer is greater than or equal to 1 nm and less than or equal to 20 nm, and a length from a bottom surface of the second semiconductor layer to a bottom surface of the third conductor in a region not overlapping with the second semiconductor layer is larger than a thickness of the second semiconductor layer.

An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.