A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer of the first region and the second region; forming a stop layer on the first region and the second region; removing the stop layer on the second region; and forming a second BBM layer on the first region and the second region.

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage. In addition, a transistor (for example, a silicon transistor or the like) capable of higher operation than a transistor including an oxide semiconductor is preferably used as a transistor in a circuit (specifically, for example, a buffer circuit, a flip-flop circuit, or the like) requiring a lower withstand voltage than the level shift circuit.

A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.

A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.