A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.

An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.

Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

A system-on-chip includes: an embedded memory module and its peripheral digital module, the embedded memory module includes at least one embedded memory cell, and the digital module includes at least one first MOS transistor and at least one standard cell; the standard cell includes at least one second MOS transistor, and the embedded memory cell includes at least one third MOS transistor, each of the first, second, and third MOS transistors includes a gate and a gate oxide layer underlying the gate, and the gate oxide layers of the second and third MOS transistors have the same thickness and are both thinner than the gate oxide layer of the first MOS transistor.

Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a semiconductor substrate, a high-Kappa dielectric layer disposed on the semiconductor substrate, a first plurality of nanostructures disposed over the high-Kappa dielectric layer, a middle dielectric layer disposed over the first plurality of nanostructures, a second plurality of nanostructures over the middle dielectric layer, a first gate structure wrapping around the first plurality of nanostructures, a second gate structure wrapping around the second plurality of nanostructures. The high-Kappa dielectric layer includes metal nitride, metal oxide, silicon carbide, graphene, or diamond.

Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.

A method for manufacturing a semiconductor structure includes: forming a channel portion on a fin portion; forming two source/drain portions on the fin portion and at two opposite sides of the channel portion, in which each of the two source/drain portions includes a first semiconductor material that is doped with dopant impurities; and forming two bottom portions each of which is disposed between the fin portion and a corresponding one of the two source/drain portions, in which each of the two bottom portions includes a second semiconductor material that is different from the first semiconductor material and that is capable of trapping the dopant impurities when the dopant impurities in the first semiconductor material diffuse toward the fin portion.