A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

A deep trench layout implementation for a semiconductor device is provided. The semiconductor device includes an isolation film with a shallow depth, an active area, and a gate electrode formed in a substrate; a deep trench isolation surrounding the gate electrode and having one or more trench corners; and a gap-fill insulating film formed inside the deep trench isolation. The one or more trench corners is formed in a slanted shape from a top view.

A deep trench layout implementation for a semiconductor device is provided. The semiconductor device includes an isolation film with a shallow depth, an active area, and a gate electrode formed in a substrate; a deep trench isolation surrounding the gate electrode and having one or more trench corners; and a gap-fill insulating film formed inside the deep trench isolation. The one or more trench corners is formed in a slanted shape from a top view.

An integrated circuit includes a first semiconductor device with an N type region biased by a first terminal and a second semiconductor device with a second region. An N type guard region is located laterally between the N type region of the first semiconductor device and the second region. A P type region is isolated in the N type guard region and is biased by a second terminal. The N type guard region is either electrically coupled to the second terminal through a resistor circuit or is characterized as floating.

Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

A semiconductor device includes a plurality of first nanosheets of a first conductive type, a plurality of second nanosheets of a second conductive type and a gate structure. The gate structure wraps the first nanosheets and the second nanosheets, wherein a first thickness of at least one of the first nanosheets is smaller than a second thickness of at least one of the second nanosheets.

A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure. The method also includes forming a gate stack wrapped around the first fin structure and the second fin structure. The method further includes simultaneously removing the sacrificial layers of the first fin structure and the second fin structure. Remaining portions of the semiconductor layers of the first fin structure form multiple first semiconductor nanostructures, and remaining portions of the semiconductor layers of the second fin structure form multiple second semiconductor nanostructures. Each of the first semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.

Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.