A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

A metal-insulator-metal capacitor includes a bottom electrode comprising a nitride of a metal, an insulator disposed on the bottom electrode and comprising an oxide of the metal, and a top electrode disposed on the insulator and comprising a nitride of the metal. Optionally, the insulator further includes an oxynitride of the metal, at least a portion of the oxynitride being characterized by a progressive change in the ratio of oxygen to nitrogen over thickness.

A charge storage fiber is described. In an embodiment, the charge storage fiber includes a flexible electrically conducting fiber, a dielectric coating on the flexible electrically conducting fiber, and a metal coating on the dielectric coating. In an embodiment, the charge storage fiber is attached to a textile-based product.

A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor.

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a semiconductor device. The device further includes an opening above the semiconductor device substantially filled with a conductive fluid, wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation. In some embodiments, the device further includes a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation. In some embodiments, the opening is configured to allow a biological sample to be introduced into the semiconductor device. In some embodiments, the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together. In some embodiments, the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array.

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.