A wiring board manufacturing method including a step A of forming a laser-modified portion in a glass substrate by applying laser light to the glass substrate from a first surface toward an opposite surface thereof; a step B of forming, on the first surface of the glass substrate, a first surface wiring layer including a hydrofluoric acid resistant metal film and a copper layer; a step C of etching a surface of the glass substrate opposite to the first surface to form a through via in the laser-modified portion and form a second surface of the glass substrate, the second surface being an opposite surface to the first surface; a through via treatment step D of removing an etching residue of glass adhered to the hydrofluoric acid resistant metal film; and a step E of forming a through electrode in the through via.

A wiring board manufacturing method including a step A of forming a laser-modified portion in a glass substrate by applying laser light to the glass substrate from a first surface toward an opposite surface thereof; a step B of forming, on the first surface of the glass substrate, a first surface wiring layer including a hydrofluoric acid resistant metal film and a copper layer; a step C of etching a surface of the glass substrate opposite to the first surface to form a through via in the laser-modified portion and form a second surface of the glass substrate, the second surface being an opposite surface to the first surface; a through via treatment step D of removing an etching residue of glass adhered to the hydrofluoric acid resistant metal film; and a step E of forming a through electrode in the through via.

An electronic device includes a substrate, a first silicon nitride film provided on the substrate, a silicon oxide film provided on the first silicon nitride film, a capacitor provided on the silicon oxide film, and an interconnect electrically connected to the capacitor. The interconnect is disposed apart from the first silicon nitride film. In a plan view, an outer perimeter of the silicon oxide film is inside an outer perimeter of the first silicon nitride film.

An electronic device includes a substrate, a first silicon nitride film provided on the substrate, a silicon oxide film provided on the first silicon nitride film, a capacitor provided on the silicon oxide film, and an interconnect electrically connected to the capacitor. The interconnect is disposed apart from the first silicon nitride film. In a plan view, an outer perimeter of the silicon oxide film is inside an outer perimeter of the first silicon nitride film.

A flexible electronic assembly includes a flexible supporting assembly, an electronic component, and a cover layer. The flexible supporting assembly includes a first surface and a second surface opposite to the first surface. In a plan view of the flexible electronic assembly, the second surface includes a plurality of protrusions and one of the protrusions includes at least one rounded corner. The electronic component is coupled to the first surface of the flexible supporting assembly. The cover layer is coupled to the electronic component.

A flexible electronic assembly includes a flexible supporting assembly, an electronic component, and a cover layer. The flexible supporting assembly includes a first surface and a second surface opposite to the first surface. In a plan view of the flexible electronic assembly, the second surface includes a plurality of protrusions and one of the protrusions includes at least one rounded corner. The electronic component is coupled to the first surface of the flexible supporting assembly. The cover layer is coupled to the electronic component.

A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.