A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer. Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Disclosed is a capacitor. The capacitor includes a plurality of capacitor units connected to each other in parallel. The capacitor unit includes a first capacitor, a second capacitor connected to the first capacitor in parallel, and a switch selectively connected to the first capacitor or the second capacitor.

In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween. The lower electrode (LEL), the dielectric film (DEC), and the upper electrodes (UEL) constitute MIM capacitors (MCA). One of the upper electrodes (UEL) and another upper electrode (UEL) that are adjacent to each other are arranged at an equal distance (Dl), without the guard ring being interposed therebetween. The upper electrodes (UEL) positioned on the outermost periphery and the guard ring (GR) positioned outside those upper electrodes UEL are arranged at a distance equal to the distance (D1) from each other.

A method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.

A method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.

A capacitor structure is provided. The capacitor structure includes a first electrode and a second electrode. The first electrode includes a first segment and a third segment. The second electrode includes a second segment and a fourth segment, the second segment is interposed between the first segment and the third segment, and the third segment is interposed between the second segment and the fourth segment. A first distance is between the first segment and the second segment, and a second distance between the second segment and the third segment. The first distance is different from the second distance.

The purpose of the invention is to form a stable oxide semiconductor TFT in a display device. The concrete structure is: A display device having a TFT substrate that includes a TFT having an oxide semiconductor layer comprising: the oxide semiconductor layer is formed on a first insulating film that is formed by a silicon oxide layer, the oxide semiconductor layer and an aluminum oxide film are directly formed on the first insulating film. The first insulating film becomes oxygen rich when the aluminum oxide film is formed on the first insulating film by sputtering. Oxygens in the first insulating film is effectively confined in the first insulating film, eventually, the oxygens diffuse to the oxide semiconductor for a stable operation of the oxide semiconductor TFT.

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

In an aspect, an interposer includes a substrate, a first metallization layer on the substrate and having a first plurality of conductive patterns, a second metallization layer having a second plurality of conductive patterns, and a via layer disposed between the first metallization layer and the second metallization layer and having a plurality of vias. At least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both may be configured to form a first inductor device and a second inductor device. The first inductor device may be electrically coupled between a first power node and a second power node of the interposer. The second inductor device may be electrically coupled between the first power node and a third power node of the interposer.