A method of forming an embedded polysilicon resistor body contact. According to the method, a transistor is formed in and above a crystalline active region that is positioned in a semiconductor layer of a multilayer semiconductor device. A resistor region is defined in single crystal semiconductor material of the semiconductor layer formed on a buried insulating layer. The resistor region is adjacent the transistor. An amorphized semiconductor material is formed in the resistor region. A barrier is formed in the amorphized semiconductor material. The barrier is between the transistor and an electrical body contact for the transistor. The amorphized semiconductor material is annealed, forming a polysilicon semiconductor. The barrier prevents the amorphized region from recrystallizing back to single crystal silicon.

A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.

A semiconductor arrangement comprising; a normally-on transistor having first and second main terminals and a control terminal, a normally-off transistor having first and second main terminals and a control terminal, the transistors connected in a cascade arrangement by a connection between one of the main terminals of the normally-on transistor and one of the main terminals of the normally-off transistor, a current-source arrangement connected to a node on the connection and configured to provide for control of the voltage at said node between the normally-on and normally-off transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor formed therein and a second semiconductor die having the normally-off transistor formed therein, the current-source arrangement formed in the first and/or second semiconductor dies.

A semiconductor arrangement comprising; a die of III-V semiconductor material; a resistor element integrated in the die, the resistor element comprising a track defined by a first implant material in the III-V semiconductor material of the die, said track electrically isolated from substantially the remainder of the die by an isolation region that surrounds the track.

An interlayer insulating film is disposed on a LOCOS oxide film covering an n-type drift region of a JFET. A polysilicon resistor having a spiral planar shape is disposed in the interlayer insulating film. A spiral wire in an outermost circumference of the polysilicon resistor is covered by a source electrode wire that extends on the interlayer insulating film. An end of the polysilicon resistor is electrically connected to a drain electrode wire. A ground terminal wire and a voltage division terminal wire are electrically connected to a spiral wire farther on an inner circumference side by one or more wires than the spiral wire. A portion farther on an inner circumference side than the spiral wire is used as a resistive element, and voltage for an input pad of the JFET is thereby divided to be taken out as a potential of the voltage division terminal wire.

A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a high voltage capacitor having a first high voltage plate, a second high voltage plate directly overlying the first high voltage plate, and a high voltage dielectric film between the first and second high voltage plates. The integrated circuit also includes a high density capacitor with a first high density plate that is about co-planar with the second high voltage plate, a second high density plate directly overlying the first high density plate, and a thin high density dielectric film positioned between the first and second high density plates.

A method of fabrication of one or more ultra-miniature piezoresistive pressure sensors on silicon wafers is provided. The diaphragm of the piezoresistive pressure sensors is formed by fusion bonding. The piezoresistive pressure sensors can be formed by silicon deposition, photolithography and etching processes.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer

An integrated circuit (IC) may include a semiconductor substrate, and a semiconductor resistor. The semiconductor resistor may include a well in the semiconductor substrate and having a first conductivity type, a first resistive region in the well having an L-shape and a second conductivity type, and a tuning element associated with the first resistive region. The IC may also include a resistance compensation circuit on the semiconductor substrate. The resistance compensation circuit may be configured to measure an initial resistance of the first resistive region, and generate a voltage at the tuning element to tune an operating resistance of the first resistive region based upon the measured initial resistance.