A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first nanosheet layer. The first nanosheet layer includes a first channel region, and a heavily doped epitaxial region of a first type. Further, the semiconductor structure includes a second nanosheet layer. The second nanosheet layer includes a second channel region, a heavily doped epitaxial region of a second type disposed above the first nanosheet layer, and a first gate surrounding the first channel region and the second channel region. Additionally, the semiconductor structure includes a protection diode. The protection diode includes a source, a drain, and a second gate. The drain is connected to the first gate, and the second gate is connected to the source.

A semiconductor device including a first stacked nanosheet Field Effect Transistor (FET), a second stacked nanosheet, a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet and an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet. An embodiment where the first stacked nanosheet and the second stacked nanosheet each include an upper stacked nanosheet and a lower stacked nanosheet, the upper stacked nanosheet and the lower stacked nanosheet each include alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another. Forming a first stacked nanosheet, forming a second stacked nanosheet, forming a MIM capacitor between the first stacked nanosheet and the second stacked nanosheet and forming an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet.

3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.

A backside reveal method includes providing a semiconductor material substrate, depositing an epitaxial high-k etch stop layer on the semiconductor material substrate, forming an integrated circuit device layer on the epitaxial high-k etch stop layer, and attaching a carrier substrate to a front side of the integrated circuit device layer. The method further includes removing a portion of a thickness of the semiconductor material substrate to leave a remaining portion of the thickness of the semiconductor material substrate, removing, by a first selective etching, the remaining portion of the semiconductor material substrate, and removing, by a second selective etching, the epitaxial high-k etch stop layer to expose a backside of the integrated circuit device layer. The epitaxial high-k etch stop layer has good lattice match and high etch selectivity relative to the semiconductor material substrate.

As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.

A method includes forming a fin structure over a bottom dielectric isolator and a substrate. The fin structure includes a bottom channel layer, a sacrificial layer over the bottom channel layer, and a top channel layer over the sacrificial layer. A dummy gate is formed across the fin structure. Portions of the fin structure not covered by the gate structure are removed to expose a top surface of the bottom dielectric isolator. First source/drain epitaxial structures are epitaxially grown over the bottom dielectric isolator and are connected to the bottom channel layer. Second source/drain epitaxial structures are epitaxially grown over the first source/drain epitaxial structures and are connected to the top channel layer. The dummy gate and the sacrificial layer are replaced with a gate structure.

A highly flexible display device and a method for manufacturing the display device are provided. A transistor including a light-transmitting semiconductor film, a capacitor including a first electrode, a second electrode, and a dielectric film between the first electrode and the second electrode, and a first insulating film covering the semiconductor film are formed over a flexible substrate. The capacitor includes a region where the first electrode and the dielectric film are in contact with each other, and the first insulating film does not cover the region.

A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface. The top surface defines a first groove. The first groove is substantially ring-shaped. The glue layer is arranged in the top surface and surrounds the first groove. A plurality of glass-frits is distributed in the glue layer.

The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500 C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.