A semiconductor device includes a metal nitride layer, a channel provided in the metal nitride layer and including a two-dimensional (2D) semiconductor material, a source electrode provided on one side of the channel, a drain electrode provided on another side of the channel, a gate insulating layer provided in the channel, and a gate electrode provided on the gate insulating layer.

A semiconductor device may include a gate electrode, a metal nitride layer on the gate electrode, a gate insulating film on the metal nitride layer, a channel on the gate insulating film, a source electrode in one side of the channel, and a drain electrode in another side of the channel.

Provided are a semiconductor device including a two-dimensional material and a manufacturing method thereof. The semiconductor device includes a channel layer containing a two-dimensional semiconductor material, a source electrode and a drain electrode provided on both sides of the channel layer, respectively, a gate insulating layer provided on the channel layer between the source electrode and the drain electrode and including a two-dimensional insulating material, an interlayer provided between the channel layer and the gate insulating layer, and a gate electrode provided on the gate insulating layer.

Provided is a semiconductor device including a two-dimensional semiconductor material. The semiconductor device includes a first channel including a first two-dimensional material layer, a second channel being apart from the first channel and including a second two-dimensional material layer, a common gate electrode between the first channel and the second channel, a first source electrode and a first drain electrode in contact with the first channel, and a second source electrode and a second drain electrode in contact with the second channel, wherein one of the first channel and the second channel is an N-type channel, and the other is a P-type channel, and the first channel and the second channel are U-shaped.

A device includes a first source/drain region including: a first metal layer including a first metal; and a conductive two-dimensional material on the first metal layer; an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material; and a gate stack on the two-dimensional semiconductor material.

Disclosed are semiconductor thin film comprising indium-selenide compound, thin film transistor comprising same and method of manufacturing ferroelectric memory comprising same. The method comprises (a) depositing at least one deposition source selected from the group consisting of indium, selenium and In.sub.2Se.sub.3 on a substrate by a thermal evaporation deposition method to form a coating layer; and (b) annealing the coating layer by heat treatment to manufacture a semiconductor thin film comprising an indium-selenide compound. The thin film transistor (TFT) manufactured based on an In.sub.xSe.sub.y channel layer using a deposition method of a thermal evaporation process according to the manufacturing method of the present disclosure has the effect of exhibiting excellent output/transfer characteristics and excellent electrical performance with high electron field effect mobility and a high on/off current ratio of 710.sup.8.

Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.

A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.