Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar extends from a first surface of a substrate toward a second surface opposite to the first surface. The first portion includes the buried gate pillar, a first gate dielectric layer at a first sidewall of the buried gate pillar and a first doped region set aside the first gate dielectric layer. A first channel is provided in the substrate between the first gate dielectric layer and the first doped region set. The second portion includes the buried gate pillar, a second gate dielectric layer at a second sidewall of the buried gate pillar and a second doped region set aside the second gate dielectric layer. A second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.

A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.

A method for fabricating a fin field-effect transistor (FinFET) device includes forming a first dielectric layer over a substrate and then etching the first dielectric layer and the substrate to form a first fin and a second fin. A second dielectric layer is formed along sidewalls of the first fin and the second fin. A protection layer is deposited over the first fin and the second fin. A portion of the protection layer and the first dielectric layer on the second fin is removed and the second fin is then recessed to form a trench. A semiconductor material layer is epitaxially grown in the trench. The protection layer is removed to reveal the first fin and the second fin.

The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve R.sub.sp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Q.sub.g for an identical device pitch to that of an alternative technology.

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.

A method for forming a semiconductor device comprises forming a first buffer layer with a first melting point on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer has a second melting point that is greater than the first melting point. Annealing process is performed that increases a temperature of the first buffer layer such that the first buffer layer partially liquefies and causes a strain in the second buffer layer to be substantially reduced.