A strain relaxed buffer layer is fabricated by melting an underlying layer beneath a strained semiconductor layer, which allows the strained semiconductor layer to elastically relax. Upon recrystallization of the underlying layer, crystalline defects are trapped in the underlying layer. Semiconductor layers having different melting points, such as silicon germanium layers having different atomic percentages of germanium, are formed on a semiconductor substrate. An annealing process causes melting of only the silicon germanium layer that has the higher germanium content and therefore the lower melting point. The silicon germanium layer having the lower germanium content is elastically relaxed upon melting of the adjoining silicon germanium layer and can be used as a substrate for growing strained semiconductor layers such as channel layers of field-effect transistors.

There is provides a method of fabricating a semiconductor device to decrease contact resistance of source/drain regions and gate electrodes and thereby improve operation performance. The method includes providing an exposed silicon region, forming a rare earth metal silicide film on the exposed silicon region, the rare earth metal silicide film contacting the silicon region, and forming a contact on the rare earth metal silicide film, the contact being electrically connected to the exposed silicon region, wherein the rare earth metal silicide film is formed by simultaneously supplying a rare earth metal and silicon to the exposed silicon region using physical vapor deposition.

A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump.

A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.