Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

The present disclosure describes forming a semiconductor structure having an isolation layer surrounding a portion of a gate structure. The semiconductor structure includes a channel structure on a substrate, a first isolation layer on the substrate and surrounding the channel structure, and a gate structure on the channel structure and the first isolation layer. The gate structure includes a first portion having a first width and a second portion having a second width less than the first width. The semiconductor structure further includes a second isolation layer on the first isolation layer and surrounding the first portion of the gate structure.

Provided are semiconductor devices and methods for fabricating such devices. An exemplary method includes forming a fin structure over a semiconductor material; forming a sacrificial layer over the semiconductor material; removing a portion of the fin structure and an overlying portion of the sacrificial layer located over the portion of the fin structure to form a trench; forming an insulation structure in the trench, wherein an adjacent portion of the sacrificial layer is adjacent an end wall of the insulation structure; removing the adjacent portion to form a cavity partially defined by the end wall; lining the cavity with a liner, wherein an end portion of the liner is located on the end wall of the insulation structure; filling the cavity with a fill material; removing the end portion of the liner to form an opening; and forming an end isolation structure in the opening.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.

A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi.sub.2, a second silicide region on the first silicide region, the second silicide region including TiSi.sub.x, and a conductive material on the second silicide region.