Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions. The sacrificial semiconductor fins are subsequently removed and replaced with insulating material to form the dummy fins.

Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor material and encapsulating the first fins and the second fins with a protective dielectric. Semiconductor material between the first fins and the second fins is etched to form trenches. A dielectric fill is employed to fill up the trenches, between the first fins and between the second fins. The first semiconductor material below the first fins and the second semiconductor material below the second fins are oxidized with the first and second fins being protected by the protective dielectric. Fins in an intermediary region between the first fins and the second fins are oxidized to form dummy fins in the intermediary region to maintain a substantially same topology across the device.

A device includes a vertical transistor comprising a first buried layer over a substrate, a first well over the first buried layer, a first gate in a first trench, wherein the first trench is formed partially through the first buried layer, and wherein a dielectric layer and the first gate are in the first trench, a second gate in a second trench, wherein the second trench is formed partially through the first buried layer, and wherein the second trench is of a same depth as the first trench, a first drain/source region and a second drain/source region formed on opposite sides of the first trench and a first lateral transistor comprising a second buried layer formed over the substrate, a second well over the second buried layer and drain/source regions over the second well.

An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin.

The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.

In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.