A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.

Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device.

A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.