A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.

An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.

A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

A method of manufacturing a semiconductor device includes forming a laminated film by laminating an N-type channel and a P-type channel on a substrate; performing patterning on the laminated film; forming a source and a drain on a front surface side; bonding a new substrate on the front surface side and removing the substrate on a back surface side; forming a source and a drain on the back surface side; and a step of forming a gate on the back surface side.

A system-on-chip includes: an embedded memory module and its peripheral digital module, the embedded memory module includes at least one embedded memory cell, and the digital module includes at least one first MOS transistor and at least one standard cell; the standard cell includes at least one second MOS transistor, and the embedded memory cell includes at least one third MOS transistor, each of the first, second, and third MOS transistors includes a gate and a gate oxide layer underlying the gate, and the gate oxide layers of the second and third MOS transistors have the same thickness and are both thinner than the gate oxide layer of the first MOS transistor.

The present disclosure provides a method of fabricating a semiconductor device, which includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate and includes a first active area, a second active area disposed outside the first active area, and a third active area disposed outside the second active area. The shallow trench isolation is disposed in the substrate to surround the active structure. Through the second active area and the third active of the active structure, the structural stability of the semiconductor device may be enhanced to improve the stress around the semiconductor device, thereby preventing from structural collapse or deformation.

An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.

A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.