A method includes identifying at least a first mask or a second mask, fabricating, by the first mask, a first conductive line, fabricating, by the second mask, a second conductive line, and fabricating, by the first mask, a third conductive line if a dimension of the first conductive line is larger than a corresponding dimension of the second conductive line, or fabricating, by the second mask, the third conductive line if the dimension of the first conductive line is less than the corresponding dimension of the second conductive line A first circuit element is coupled to a second circuit element by at least the third conductive line, and the first circuit element is separated from the second circuit element by a predetermined distance.

An integrated circuit (IC) device includes a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to a first power supply node, and a second terminal electrically coupled to a second power supply node. The second transistor includes a gate terminal configured to receive the control signal, and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to, in response to the control signal, connect or disconnect the first and second power supply nodes.

A semiconductor device includes a first memory column group including a plurality of memory columns in which a plurality of bit cells are disposed; and a first peripheral column group including a plurality of peripheral columns in which a plurality of standard cells are disposed, wherein the plurality of standard cells are configured to perform an operation of reading/writing data from/to the plurality of bit cells through a plurality of bit lines, wherein the first memory column group and the first peripheral column group correspond to each other in a column direction, and wherein at least one of the plurality of peripheral columns has a cell height different from cell heights of the other peripheral columns, the cell height being measured in a row direction in which a gate line is extended.

A semiconductor module includes an IGBT device, and a MISFET device that composes a parallel circuit together with the IGBT device. The semiconductor module generates a drain current of the MISFET device in a voltage range less than a built-in voltage of the IGBT device and generates a collector current of the IGBT device and a drain current of the MISFET device in a voltage range equal to or more than the built-in voltage.

Techniques for providing a representation of densities of layer material in an integrated circuit layout design without revealing actual layout design data to protect a vendor's proprietary design data are described. The representation of the density information is used to reduce or eliminate density violations at borders of distinct portions of the integrated circuit design. By exchanging standardized data in a density view database, the techniques described herein can be independent of the vendor. A method for manufacturing an integrated circuit includes generating a design density view database representing a first integrated circuit layout design by using layer density information associated with the first integrated circuit layout design as a proxy for actual layout design information.

A semiconductor integrated circuit, a system on chip and an electronic element are provided. The semiconductor integrated circuit includes a semiconductor substrate having a first region, and a second region, a first power rail extending in a first direction on the first region and connected to an impurity region of a first transistor to provide a first voltage, a second power rail extending in the first direction on the first region and connected to the first transistor to provide a second voltage, a third power rail extending in the first direction on the second region and connected to an impurity region of a second transistor to provide the first voltage, a fourth power rail extending in the first direction on the second region and connected to the second transistor to provide a third voltage, and a first conductor connecting the first power rail with the third power rail.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.

An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.

An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.