An integrated circuits (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.

An integrated circuits (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.

A semiconductor device including a semiconductor substrate. A first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. A CA layer forms a local interconnect layer electrically connected to one of the source and the drain of the first transistor. A CB layer forms a local interconnect layer electrically connected to the gate of one of the first transistor and the second transistor. An end of the CB layer is disposed at a center of the CA layer

A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method further includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell, and a height of the second cell is different from a height of the first cell. The method further includes forming a plurality of gate structures extending across each of the first active region and the plurality of second active regions. The method further includes removing a first portion of a first gate structure of the plurality of gate structures at an interface between the first cell and the second cell, wherein the first portion of the first gate structure is between the first active region and the plurality of second active regions.

An I/O circuit is formed by combining plural types of standard cells contained in a cell library. For example, the standard cell includes a first element forming region having, formed therein, protection target elements each having a gate electrically connected to an external terminal, a second element forming region arranged in immediate proximity to the external terminal and having first protection elements formed therein, and a third element forming region arranged between the first and second element forming regions and having transistors formed therein. The transistors each have a drain connected to gates of the protection target elements and a source, gate, and back gate all connected to a power supply or ground terminal, thus functioning as a second protection element.

An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

A content addressable memory has many elements in one memory cell; thus, the area of one memory cell tends to be large. In view of the above, it is an object of an embodiment of the present invention to reduce the area of one memory cell. Charge can be held with the use of a channel capacitance in a reading transistor (capacitance between a gate electrode and a channel formation region). In other words, the reading transistor also serves as a charge storage transistor. One of a source and a drain of a charge supply transistor is electrically connected to a gate of the reading and charge storage transistor.

Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a conductive layer, which is disposed between a first node and a second node in a semiconductor chip, and which has a width that is at least a first threshold value but not more than a second threshold value, the first threshold value and the second threshold value being less than the minimum width according to the design rules that can ensure that the conductive layer is patterned such that the first node and the second node are electrically short-circuited, and a reader which provides an identification key by identifying if there is a short circuit between the first node and the second node.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.