A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm.sup.3.

A method includes selectively degrading a current capacity of a first finned-field-effect-transistor (finFET) relative to a second finFET by forming a material on a fin of the first finFET to increase a current resistance of the first finFET. The second finFET is electrically connected to the first finFET in a circuit such that a current flow through the second finFET is a multiple of a current flow through the first finFET.

In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more ART trenches, and recessing the first semiconductor material down into the ART trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures. The method further includes epitaxially growing a second semiconductor material on top of the first semiconductor material and substantially filling the ART trenches to form a semiconductor fin that comprises an upper portion comprising the second semiconductor material and a lower portion comprising the first semiconductor material.

The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.

Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.