Inside an IGBT using GaN or SiC, light having an energy of approximately 3 [eV] is generated. Therefore, defects are caused in the gate insulating film of the IGBT. Furthermore, the charge trapped at a deep level becomes excited and moves to the channel region, thereby causing the gate threshold voltage to fluctuate from the predetermined value. Provided is a semiconductor device including a normally-ON semiconductor element that includes a first semiconductor layer capable of conductivity modulation and a first gate electrode, but does not include a gate insulating film between the first gate electrode and the first semiconductor layer; and a normally-OFF semiconductor element that includes a second semiconductor layer, a second gate electrode, and a gate insulating film between the second semiconductor layer and the second gate electrode. The normally-ON semiconductor element and the normally-OFF semiconductor element are connected in series.

A p-type base region, n.sup.+-type source region, p.sup.+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.

An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0 as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0 in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.

In certain embodiments, a semiconductor device includes a plurality of semiconductor chips. Each semiconductor chip comprises a semiconductor body having a first side and a second side opposite the first side, a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate, and a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side. The semiconductor device further includes a plurality of separation trenches each separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips.

A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

A method of forming an SiC crystal including placing in an insulated graphite container a seed crystal of SiC, and supporting the seed crystal on a shelf, wherein cushion rings contact the seed crystal on a periphery of top and bottom surfaces of the seed crystal, and where the graphite container does not contact a side surface of the seed crystal; placing a source of Si and C atoms in the insulated graphite container, where the source of Si and C atoms is for transport to the seed crystal to grow the SiC crystal; placing the graphite container in a furnace; heating the furnace; evacuating the furnace; filling the furnace with an inert gas; and maintaining the furnace to support crystal growth to thereby form the SiC crystal.

A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.