A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

A method for forming a graphene layer on a semiconductor substrate, a semiconductor diode utilizing the method for graphene layer formation, and an optoelectronic semiconductor device also utilizing the method for graphene layer formation are provided. An example method for disposing a graphene layer on a semiconductor substrate may include depositing a metal catalyst layer on a top surface of the semiconductor substrate and patterning the metal catalyst layer, such that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures. The method may further include facilitating a graphene growth process on an exposed surface of the one or more metal catalyst layer structures, wherein the graphene growth process forms the graphene layer on the exposed surfaces of the one or more metal catalyst layer structures.

An embodiment semiconductor device includes a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction and a termination region at an end of the conductive region in the first direction, wherein the termination region includes an n+ type substrate, an n type layer disposed on an upper surface of the n+ type substrate and having a plurality of first trenches opening upward in the third direction, and a lower gate runner covering the plurality of first trenches and disposed on an upper surface of the n type layer.

An embodiment semiconductor device includes an N type layer having a trench therein, a P type region within the N type layer, an N+ type region within the P type region, a gate electrode within the trench including a first gate electrode having an upper surface lower than an upper surface of the P type region and a second gate electrode having an upper surface lower than the upper surface of the first gate electrode, and source and drain electrodes insulated from the gate electrode, wherein the N+ type region includes a first N+ type region on a side of the first gate electrode and having a lower surface lower than the upper surface of the first gate electrode and a second N+ type region on a side of the second gate electrode and having a lower surface lower than the lower surface of the first N+ type region.

The disclosure relates to a semiconductor die with a semiconductor device in a semiconductor body, the semiconductor body comprising a silicon carbide substrate; an epitaxial silicon carbide layer system on a first side of the silicon carbide substrate; an interruption layer; wherein the interruption layer is embedded either into the silicon carbide substrate or into the epitaxial silicon carbide layer system, in each case at a vertical distance from the first side of the silicon carbide substrate.

A method of manufacturing a silicon carbide device includes forming a transfer foil that includes a porous silicon carbide layer. A composite substrate is formed that includes the transfer foil and a support substrate. The transfer foil and the support substrate are brought into contact with each other and connected to each other. An epitaxial layer is formed on a side of the porous silicon carbide layer opposite to the support substrate. The composite substrate is divided into a device substrate and a reclaim substrate. The device substrate includes the epitaxial layer and the reclaim substrate includes the support substrate.

A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500 C. and 2600 C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.