A superlattice composite structure includes a first superlattice stack layer and a second superlattice stack layer. The first superlattice stack layer includes a plurality of first units stacked along a vertical direction. Each of the first units includes an aluminium nitride (AlN) layer, an aluminium gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer stacked in sequence along the vertical direction. The second superlattice stack layer is stacked with the first superlattice stack layer along the vertical direction. The second superlattice stack layer includes a plurality of second units stacked along the vertical direction. Each of the second units includes another AlN layer, another AlGaN layer and another GaN layer stacked in sequence along the vertical direction.

The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

A microelectronic device that is radiation hardened through the incorporation of a quantum structure getter (QSG) is provided. The device, such as a field effect transistor (FET) includes a conductive channel and a material stack comprising: a capping layer, one or more barrier layers comprising a high band gap, one or more quantum structures comprising a small band gap, and a substrate. The quantum structures are positioned in close proximity to the conductive channel to form a quantum well charge getter. The getter forms a low energy area beneath the FET, which traps and confines electron-hole pair wave functions produced from ionizing radiation, causing the wave functions overlap, recombine, and produce light emission. The quantum structures getter the wave functions, which reduces the ionized photocurrent that reaches the conducting channel, thereby hardening the microelectronic device against ionizing radiation.

A transistor can include a substrate, an epitaxial oxide layer on the substrate, and a gate layer. The substrate can include a first crystalline material. The epitaxial oxide layer can include a second oxide material including: Li and one of Ni, Al, Ga, Mg, Zn and Ge; or Ni and one of Li, Al, Ga, Mg, Zn and Ge; or Mg and one of Ni, Al, Ga, and Ge; or Zn and one of Ni, Al, Ga, and Ge. The gate layer can include a third oxide material. A bandgap of the third oxide material of the gate can be wider than a bandgap of the second oxide material of the epitaxial oxide layer. The transistor can also include a source electrical contact coupled to the epitaxial oxide layer, a drain electrical contact coupled to the epitaxial oxide layer, and a first gate electrical contact coupled to the gate layer.

An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

According to this GaN-based HFET, resistivity of a semi-insulating film forming a gate insulating film is 3.910.sup.9cm. The value of this resistivity is a value derived when the current density is 6.2510.sup.4 (A/cm.sup.2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity =3.910.sup.9cm, a withstand voltage of 1000 V can be obtained. Meanwhile, the withstand voltage abruptly drops as the resistivity of the gate insulating film exceeds 1 10.sup.11cm, and the gate leak current increases when the resistivity of the gate insulating film drops below 1 10.sup.7cm.

A semiconductor device includes a semiconductor body having opposite first and second surfaces, a drift or base zone in the semiconductor body and an oxygen diffusion barrier in the semiconductor body. The drift or base zone is located between the first surface and the oxygen diffusion barrier and directly adjoins the oxygen diffusion barrier. The semiconductor device further includes first and second load terminal contacts. At least one of the first and the second load terminal contacts is electrically connected to the semiconductor body through the first surface.

A semiconductor apparatus (10) includes: a layered structure (100) that includes double junction structures that have a first junction (151, 153) where a wide-bandgap layer (102, 104) and a narrow-bandgap layer (101, 103, 105) are layered on each other and a second junction (152, 154) where a narrow-bandgap layer (101, 103, 105) and a wide-bandgap layer (102, 104) are layered on each other, and electrode semiconductor layers (110, 120) are joined to each layer of the layered structure. Each double junction structure includes a pair of a first region (131, 133) that has negative fixed charge and a second region (132, 134) that has positive fixed charge. The first region is closer to the first junction than to a center of the wide-bandgap layer. The second region is closer to the second junction than to the center of the wide-bandgap layer. A 2DEG or a 2DHG is formed at each junction. The semiconductor apparatus functions as an electric energy storage device such as a capacitor.