Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

An embodiment of a method of manufacturing a semiconductor device includes forming an oxygen diffusion barrier on a first surface of a Czochralski or magnetic Czochralski silicon substrate. A silicon layer is formed on the oxygen diffusion barrier. P-doped and n-doped semiconductor device regions are formed in the silicon layer. The method also includes forming first and second load terminal contacts.

A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.

A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.

A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material Al.sub.xIn.sub.yGa.sub.zN in which 0x1, 0y1, and 0z1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

To provide a resonant tunneling diode and a terahertz oscillator capable of further performance improvement. The resonant tunneling diode includes: a multi-quantum well structure that is composed of a group-III nitride semiconductor; a first electrode that is connected to one of sides of the multi-quantum well structure; and a second electrode that is connected to the other side of the multi-quantum well structure. The multi-quantum well structure includes a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, and a third barrier layer, which are arranged in order from the first electrode toward the second electrode. The first barrier layer, the second barrier layer, and the third barrier layer have a thickness through which a carrier can pass by a tunneling effect. The first quantum well layer and the second quantum well layer each have a potential gradient by spontaneous polarization or a sum of spontaneous polarization and piezoelectric polarization, and have mutually different thicknesses. The first quantum well layer and the second quantum well layer have compositions with different magnitudes of potential energy.

Silicon germanium (SiGe)/silicon containing superlattice structures and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of germanium throughout the layer. For example, in some embodiments, for each SiGe layer there is a core SiGe film with a low Ge content and two thinner SiGe layers or cladding layers positioned on opposing sides of the core SiGe film with each of the SiGe cladding layers having a higher Ge content then the core SiGe film. Various embodiments provide for SiGe layers having a germanium depth profile enabling strained SiGe superlattice deposition on Si{110} substrates.