A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a Group III-N semiconductor stack including a plurality of layers of Group III-N semiconductor layers above the superlattice layer.

A method for making a semiconductor device may include forming a first superlattice layer on a semiconductor substrate. The first superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a first device layer on the first superlattice layer and comprising silicon, forming a second device layer on the first superlattice layer laterally adjacent the first device layer, with the second device layer comprising a Group III-N semiconductor, forming a first device on the first device layer, and forming a second device on the second device layer.

A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a piezoelectric layer on the superlattice layer and comprising a Group III-N semiconductor.

A method for making a semiconductor device may include forming a superlattice layer on a first substrate and including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a Group III-N semiconductor stack comprising a plurality of layers of Group III-N semiconductor layers above the superlattice layer, and separating the Group III-N semiconductor stack from the first substrate at the superlattice layer.

A method for making a semiconductor device may include forming a semiconductor substrate, and forming a superlattice layer on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers may including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a Group III-N semiconductor stack comprising a plurality of layers of Group III-N semiconductor layers above the superlattice layer.

A semiconductor device may include a semiconductor substrate and a first superlattice layer on the semiconductor substrate. The first superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first device layer on the first superlattice layer and comprising silicon, a second device layer on the first superlattice layer laterally adjacent the first device layer, with the second device layer comprising a Group III-N semiconductor, a first device on the first device layer, and a second device on the second device layer.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

An epitaxial wafer and a semiconductor memory device, the epitaxial wafer including a semiconductor substrate having a front surface and a rear surface opposite to each other; a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate; and a multi-stack on and entirely covering a surface of the SRB layer, wherein the SRB layer includes a silicon germanium (SiGe) epitaxial layer including germanium (Ge) at a first concentration of about 2.5 at % to about 18 at %, and the multi-stack has a superlattice structure in which a plurality of silicon (Si) layers and a plurality of SiGe layers are alternately provided.

One or more semiconductor structures comprising a hole draining structure are provided. A semiconductor structure has a first layer formed over a substrate. The first layer has a first concentration of a metal material. The semiconductor structure has a second layer formed over the first layer. The second layer has a second concentration of the metal material different than the first concentration of the metal material. The semiconductor structure has a hole draining structure formed from a superlattice formed between the first layer and the second layer. The hole draining structure has a concentration of the metal material increasing towards the first layer and decreasing towards the second layer.

A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.