Patent classifications
H10D62/815
Optoelectronic integrated circuit
A semiconductor device employs an epitaxial layer arrangement including a first ohmic contact layer and first modulation doped quantum well structure disposed above the first ohmic contact layer. The first ohmic contact layer has a first doping type, and the first modulation doped quantum well structure has a modulation doped layer of a second doping type. At least one isolation ion implant region is provided that extends through the first ohmic contact layer. The at least one isolation ion implant region can include oxygen ions. The at least one isolation ion implant region can define a region that is substantially free of charge carriers in order to reduce a characteristic capacitance of the device. A variety of high performance transistor devices (e.g., HFET and BICFETs) and optoelectronic devices can employ this device structure. Other aspects of wavelength-tunable microresonantors and related semiconductor fabrication methodologies are also described and claimed.
Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure
The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.
Semiconductor device, method of manufacturing the same and electronic device including the same
A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.
Conformal oxidation for gate all around nanosheet I/O device
Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.
Device with transparent and higher conductive regions in lateral cross section of semiconductor layer
A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
PHOTONIC INTEGRATED CIRCUITS BASED ON QUANTUM CASCADE STRUCTURES
Photonic integrated circuits (PICs) are based on quantum cascade (QC) structures. In embodiment methods and corresponding devices, a QC layer in a wave confinement region of an integrated multi-layer semiconductor structure capable of producing optical gain is depleted of free charge carriers to create a low-loss optical wave confinement region in a portion of the structure. Ion implantation may be used to create energetically deep trap levels to trap free charge carriers. Other embodiments include modifying a region of a passive, depleted QC structure to produce an active region capable of optical gain. Gain or loss may also be modified by partially depleting or enhancing free charge carrier density. QC lasers and amplifiers may be integrated monolithically with each other or with passive waveguides and other passive devices in a self-aligned manner. Embodiments overcome challenges of high cost, complex fabrication, and coupling loss involved with material re-growth methods.
Superlattice materials and applications
A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.
Semiconductor structures
The present application provides a semiconductor structure. The semiconductor structure includes a channel layer and a barrier layer provided on the channel layer. The barrier layer includes multiple barrier layers arranged in a stack, the multiple barrier sub-layers include at least three barrier sub-layers, and Al component proportions of the multiple barrier sub-layers vary along a growth direction of the barrier layer for at least one up-and-down fluctuation.
Solar Cells Having Nanowire Titanium Oxide and/or Silicon Carbide Cores and Graphene Exteriors
An apparatus comprising a plurality of solar cells that each comprise a nanowire titanium oxide core having graphene disposed thereon. By one approach this plurality of solar cells can comprise, at least in part, a titanium foil having the plurality of solar cells disposed thereon wherein at least a majority of the solar cells are aligned substantially parallel to one another and substantially perpendicular to the titanium foil. Such a plurality of solar cells can be disposed between a source of light and another modality of solar energy conversion such that both the solar cells and the another modality of solar energy conversion generate electricity using a same source of light.
Normally-Off Field Effect Transistor
A normally-off transistor with a high operating voltage is provided. The transistor can include a barrier above the channel and an additional barrier layer located below the channel. A source electrode and a drain electrode are connected to the channel and a gate electrode is connected to the additional barrier layer located below the channel. The bandgap for each of the barrier layers can be larger than the bandgap for the channel. A polarization charge induced at the interface between the additional barrier layer below the channel and the channel depletes the channel. A voltage can be applied to the bottom barrier to induce free carriers into the channel and turn the channel on.