A semiconductor device includes: an active region extending on a substrate in a first direction; a gate structure intersecting the active region and extending on the substrate in a second direction; and a source/drain region on the active region on at least one side of the gate structure. The source/drain region may include a first epitaxial layer on the active region and including impurities of a first conductivity type in a first concentration, a second epitaxial layer on the first epitaxial layer and including the impurities of the first conductivity type in a second concentration, and a first barrier layer between the first epitaxial layer and the second epitaxial layer, wherein the first barrier layer includes doped oxygen.

A semiconductor structure can comprise a plurality of first semiconductor layers comprising wide bandgap semiconductor layers, a narrow bandgap semiconductor layer, and a chirp layer between the plurality of first semiconductor layers and the narrow bandgap semiconductor layer. The values of overlap integrals between different electron wavefunctions in a conduction band of the chirp layer can be less than 0.1 for intersubband transition energies greater than 1.0 eV, and/or the values of overlaps between electron wavefunctions and barrier centers in a conduction band of the chirp layer can be less than 0.4 nm.sup.1, when the structure is biased at an operating potential. The chirp layer can comprise a short-period superlattice with alternating wide bandgap barrier layers and narrow bandgap well layers, wherein the thickness of the barrier layers, or the well layers, or the thickness of both the barrier and well layers changes throughout the chirp layer.

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.

A method for making an electronic device may include forming a semiconductor region comprising a semiconductor layer and at least one non-semiconductor monolayer constrained within a crystal lattice of the silicon layer. The method may also include forming a plurality of spaced apart alternating N-type and P-type regions within the semiconductor region, forming at least one electrode associated with the semiconductor region, and poling the semiconductor region to align a net electrical dipole moment thereof using the plurality of spaced apart alternating N-type and P-type regions. The poled region may include a superlattice.

A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a gate oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.

According to one embodiment, a nitride semiconductor includes a nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N, a second nitride region including Al.sub.x2Ga.sub.1-x2N, and a third nitride region including Al.sub.x3Ga.sub.1-x3N. The second nitride region is provided between the first and third nitride regions in a first direction from the first nitride region to the second nitride region. The second nitride region includes carbon and oxygen. The first nitride region does not include carbon, or a second carbon concentration in the second nitride region is higher than a first carbon concentration in the first nitride region. The second carbon concentration is higher than a third carbon concentration in the third nitride region. A ratio of a second oxygen concentration in the second nitride region to the second carbon concentration is not less than 1.010.sup.4 and not more than 1.410.sup.3.

A method of forming a semiconductor device, the method including forming a superlattice structure on a substrate, the superlattice structure including a plurality of first layers and a corresponding plurality of second layers, the first layers and the second layers being alternatingly arranged in a plurality of stacked pairs; forming one or more gate and gate spacers in a gate region on the substrate; forming a plurality of nanosheets from the superlattice structure; filling the corresponding plurality of voids with a plurality of dummy dielectric interlayers; etching the plurality of nanosheets between the one or more gate and gate spacers to form one or more source regions and one or more drain regions; forming an inner spacer on the plurality of dummy dielectric interlayers; and depositing a source material in the one or more source regions and a drain material in the one or more drain regions.