Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

A VDMOS includes a substrate; an epitaxial layer; first and second trenches defined in the epitaxial layer; a shielding gate and a control gate formed in the trenches; a body region formed at the epitaxial layer and between the first and second trenches; a N+ source region formed at the body region; a distinct doping region formed in the epitaxial layer underneath the body region, extending towards bottoms of the trenches; a channel defined between the N+ source region and epitaxial layer adjacent to the trenches; an insulating layer defining a contact hole extending into the body region and the first trench; a P+ body pickup region formed in the body region corresponding to the contact hole; and a metal layer haying a butting contact filled in the contact hole, connecting the N+ source region, P+ body pickup region, and control gate and/or shielding gate in the first trench.

A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source region and the drift region in the first direction, a plurality of planar insulation field plates disposed over the drift region and spaced apart from each other in a second direction, a plurality of trench insulation field plates disposed in the drift region, a gate insulation layer formed over the channel region, and a gate electrode formed over the gate insulation layer. Each of the trench insulation field plates is disposed between the planar insulation field plates in the second direction.

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

A method for fabricating a semiconductor device is disclosed. A plurality of trenches is formed at a predetermined cell pitch in an upper surface portion of a substrate. A first insulation film is formed on the substrate. A gate electrode is formed within each trench, wherein the gate electrode partially fills each trench. A first conductivity type region is formed in the upper surface portion of the substrate between the trenches. A second conductivity type region is formed in a side surface of the substrate between the trenches and the first conductivity type region. A second insulation film is formed covering the gate electrode within each trench, wherein an upper surface of the second insulation film is positioned lower than an upper surface of the substrate. A source metal layer is formed on the second insulation film. The source metal layer is electrically connected to the first conductivity type region and the second conductivity type region.

It is an object to provide the techniques capable of restraining avalanche breakdown at cells opposite to a corner portion of a gate pad. A MOSFET is provided with a corner cell, which is disposed in a region opposite to a corner portion of a gate pad in a planar view, and an internal cell, which is disposed in a region in the opposite side of the gate pad with respect to the corner cell. In a contour shape of the corner cell, a longest distance among distances each of which is shortest distance between a longest side and each of sides opposite to the longest side is equal to or less than two times of a length of one of equal sides or a short side of the internal cell.

The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.