Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

A semiconductor device and a method of manufacturing the semiconductor device includes forming a first and a second gate electrode on a semiconductor substrate, forming a first and a second insulator on the first and second gate electrodes, forming a third insulator on the second insulator, a first thickness of the third insulator on the first gate electrode being different than a second thickness of the third insulator on the second gate electrode, and etching-back the first, second and third insulators to form a first spacer beside the first gate electrode and a second spacer beside the second gate electrode. Herein, a horizontal length of the first spacer being contacted with a surface of the semiconductor substrate is different from a horizontal length of the second spacer being contacted with a surface of the semiconductor substrate.

The present disclosure relates to a semiconductor apparatus, a fabrication method thereof, and a memory system. In the present disclosure, different semiconductor devices (e.g., a high-voltage device and a low-voltage device) of a semiconductor apparatus are provided with gate spacers of different thicknesses by two dielectric deposition operations. Due to the use of the two dielectric deposition operations, the present disclosure can both provide a high-voltage device with a gate spacer having a relatively larger thickness and provide a low-voltage device with a gate spacer having a relatively smaller thickness, such as a thin gate spacer having a thickness less than 8 nm.

An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.

A semiconductor device may include the following elements: a fin member including a first doped portion, a second doped portion, and a semiconductor portion positioned between the first doped portion and the second doped portion; a composite structure including a conductor and an insulator positioned between the conductor and the semiconductor portion in a first direction; a first spacer having a first dielectric constant and positioned close to the second doped portion; a second spacer having a second dielectric constant and positioned close to the first doped portion; and a third spacer having a third dielectric constant. The second spacer is positioned between the third spacer and the fin member in the first direction. The composite structure is positioned between the first spacer and the second spacer. The first dielectric constant is less than at least one of the second dielectric constant and the third dielectric constant.

A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a first dielectric layer having a first thickness on the semiconductor substrate, forming a first opening having a first width in the first dielectric layer and exposing a surface of the semiconductor substrate, forming a spacer on opposite sidewalls of the first opening, forming a second dielectric layer having a second thickness on the exposed surface of the semiconductor substrate in a middle region of the first opening, removing the spacer to form a second opening having a first opening portion and a second opening portion on opposite sides of the second dielectric layer, and forming a third dielectric layer having a third thickness on the first and second opening portions of the second opening. The third thickness is smaller than the first thickness and the second thickness.

There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.